ngdbuild -p xc95216-15-pq160 -uc f:\fpanel2\fpanel2.ucf -dd .. f:\fpanel2\fpanel2.edn fpanel2.ngd ngdbuild: version M1.5.25 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc95216-15-pq160 -uc f:\fpanel2\fpanel2.ucf -dd .. f:\fpanel2\fpanel2.edn fpanel2.ngd Launcher: Executing edif2ngd "f:\fpanel2\fpanel2.edn" "F:\fpanel2\xproj\ver3\fpanel2.ngo" edif2ngd: version M1.5.25 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Writing the design to "F:/fpanel2/xproj/ver3/fpanel2.ngo"... Reading NGO file "F:/fpanel2/xproj/ver3/fpanel2.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "f:/fpanel2/fpanel2.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "fpanel2.ngd" ... Writing NGDBUILD log file "fpanel2.bld"... NGDBUILD done. ================================================== hitop -f fpanel2.ngd -d fpanel2 -s -l fpanel2.log -o fpanel2 Optimizer/Partitioner: version M1.5.25 (c) Copyright 1989-1997 Xilinx Inc. All rights reserved. Reading fpanel2.ngd WARNING:xr5030 - Constant signal value '1' drives output signal 'periph_req'. Considering device XC95216-PQ160. Flattening design.. Multi-level logic optimization. .. Timing optimization. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 150 equations into 12 function blocks................................................................................................................. Design fpanel2 has been optimized and fit into device XC95216-15-PQ160. ================================================== taengine -f fpanel2 -l fpanel2.tim Timing Report Generator: version M1.5.25 (c) Copyright 1989-1997 Xilinx Inc. All rights reserved. Path tracing .................... The number of paths traced: 3070. Generating performance summary ... WARNING:hi434 - We have detected that a large number of internal signals may be switching at the same time. To avoid potential simultaneous switching/ground bounce issues, please contact Xilinx customer support for more information. Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock int_strobe ... Cycle time table for clock tp3 ... Cycle time table for clock tp1 ... Cycle time table for clock sw_rotary1_Q.Q ... Cycle time table for clock sw_rotary2_Q.Q ... Cycle time table for clock sw_rotary0_Q.Q ... Cycle time table for clock sw_start_d2_Q.Q ... Cycle time table for clock tp4 ... Cycle time table for clock clk7d5 ... fpanel2.tim has been created. ================================================== hplusas6 -i fpanel2 -s -a -l fpanel2.log -o fe_temp Fitter1: version M1.5.25 (c) Copyright 1989-1997 Xilinx Inc. All rights reserved. ================================================== hprep6 -i fe_temp -r jed -a -l fpanel2.log -n fpanel2 Programming File Generator: version M1.5.25 (c) Copyright 1989-1997 Xilinx Inc. All rights reserved. Signature length is limited to 4 characters, using 'fpan'. ================================================== xcpy fpanel2.jed f:\fpanel2\fpanel2.jed