Performance Summary Report -------------------------- Design: power Device: XC9572-15-PC84 Program: Timing Report Generator: version M1.5.19 Date: Thu Nov 05 22:33:44 1998 Performance Summary: Pad to Pad (tPD) : 28.5ns (1 macrocell levels) Pad 'relay4' to Pad 'pdata4' Clock net 'clk7d5' path delays: Clock Pad to Output Pad (tCO) : 41.5ns (2 macrocell levels) Clock Pad 'clk7d5' to Output Pad 'pdata4' (GCK) Clock to Setup (tCYC) : 26.5ns (1 macrocell levels) Clock to Q, net 'rev_req_cnt0_Q.Q' to TFF Setup(D) at 'ack_rev_Q.D' (GCK) Target FF drives output net 'ack_rev_Q.Q' Setup to Clock at the Pad (tSU) : 16.5ns (0 macrocell levels) Data signal 'rev_req' to DFF D input Pin at 'rev_req_sync_Q.D' Clock pad 'clk7d5' (GCK) Minimum Clock Period: 26.5ns Maximum Internal Clock Speed: 37.7Mhz (Limited by Cycle Time) -------------------------------------------------------------------------------- Pad to Pad (tPD) (nsec) \ From e r r r r r r r r \ c e e e e e e e e \ p l l l l l l l l \ _ a a a a a a a a \ m y y y y y y y y \ o 0 1 2 3 4 5 6 7 \ d \ e To \------------------------------------------------------ pdata0 28.5 pdata1 28.5 pdata2 28.5 pdata3 28.5 pdata4 28.5 pdata5 28.5 pdata6 28.5 pdata7 28.5 xflag 28.5 -------------------------------------------------------------------------------- Clock Pad to Output Pad (tCO) (nsec) \ From c \ l \ k \ 7 \ d \ 5 \ \ \ \ \ \ To \------ ack_rev 13.0 our_addr 13.0 pdata0 41.5 pdata1 41.5 pdata2 41.5 pdata3 41.5 pdata4 41.5 pdata5 41.5 pdata6 41.5 pdata7 41.5 periph_ack 13.0 periph_clk 13.0 periph_req 38.5 relay0 13.0 relay1 13.0 relay2 13.0 relay3 13.0 relay4 13.0 relay5 13.0 relay6 13.0 relay7 13.0 rev_req_cnt0 13.0 rev_req_cnt1 13.0 rev_req_sync 13.0 -------------------------------------------------------------------------------- Setup to Clock at Pad (tSU) (nsec) \ From c \ l \ k \ 7 \ d \ 5 \ \ To \------ ecp_mode 16.5 host_ack 16.5 host_clk 16.5 pdata0 16.5 pdata1 16.5 pdata2 16.5 pdata3 16.5 pdata4 16.5 pdata5 16.5 pdata6 16.5 pdata7 16.5 rev_req 16.5 -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: clk7d5) \ From a b b d h h h h o p \ c y y a o o o o u a \ k t t t s s s s r r \ _ e e a t t t t _ _ \ r _ _ _ _ _ _ _ a r \ e c c m c c c c d x \ v n n o l l l l d _ \ _ t t d k k k k r r \ Q 0 1 e _ _ _ _ _ i \ . _ _ _ c c d d Q s \ Q Q Q Q n n 1 2 . i \ . . . t t _ _ Q n \ Q Q Q 0 1 Q Q g \ _ _ . . _ \ Q Q Q Q Q \ . . . \ Q Q Q To \------------------------------------------------------------ ack_rev_Q.D 19.0 26.5 byte_cnt0_Q.D 19.0 19.0 19.0 byte_cnt1_Q.D 19.0 19.0 19.0 19.0 data_mode_Q.D 26.5 19.0 host_clk_cnt0_Q.D 19.0 19.0 19.0 26.5 host_clk_cnt1_Q.D 19.0 19.0 19.0 26.5 host_clk_d1_Q.D 26.5 host_clk_d2_Q.D 26.5 our_addr_Q.D 26.5 19.0 19.0 par_rx_rising_Q.D periph_ack_Q.D 26.5 26.5 26.5 26.5 26.5 periph_clk_Q.D 26.5 26.5 26.5 26.5 26.5 26.5 reg_num0_Q.D 26.5 19.0 reg_num1_Q.D 26.5 19.0 reg_num2_Q.D 26.5 19.0 relay0_Q.D 26.5 26.5 26.5 26.5 26.5 relay1_Q.D 26.5 26.5 26.5 26.5 26.5 relay2_Q.D 26.5 26.5 26.5 26.5 26.5 relay3_Q.D 19.0 19.0 19.0 19.0 19.0 relay4_Q.D 19.0 19.0 19.0 19.0 19.0 relay5_Q.D 19.0 19.0 19.0 19.0 19.0 relay6_Q.D 19.0 19.0 19.0 19.0 19.0 relay7_Q.D 26.5 26.5 26.5 26.5 26.5 rev_req_cnt0_Q.D rev_req_cnt1_Q.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: clk7d5) \ From p p r r r r r r r r \ e e e e e e e e e e \ r r g g g l l l l l \ i i _ _ _ a a a a a \ p p n n n y y y y y \ h h u u u 0 1 2 3 4 \ _ _ m m m _ _ _ _ _ \ a c 0 1 2 Q Q Q Q Q \ c l _ _ _ . . . . . \ k k Q Q Q Q Q Q Q Q \ _ _ . . . \ Q Q Q Q Q \ . . \ Q Q \ \ \ To \------------------------------------------------------------ ack_rev_Q.D 26.5 26.5 26.5 byte_cnt0_Q.D byte_cnt1_Q.D data_mode_Q.D 26.5 host_clk_cnt0_Q.D host_clk_cnt1_Q.D host_clk_d1_Q.D host_clk_d2_Q.D our_addr_Q.D par_rx_rising_Q.D 26.5 periph_ack_Q.D 19.0 periph_clk_Q.D 19.0 reg_num0_Q.D 19.0 reg_num1_Q.D 19.0 reg_num2_Q.D 19.0 relay0_Q.D 26.5 26.5 26.5 19.0 relay1_Q.D 26.5 26.5 26.5 19.0 relay2_Q.D 26.5 26.5 26.5 19.0 relay3_Q.D 19.0 19.0 19.0 19.0 relay4_Q.D 19.0 19.0 19.0 19.0 relay5_Q.D 19.0 19.0 19.0 relay6_Q.D 19.0 19.0 19.0 relay7_Q.D 26.5 26.5 26.5 rev_req_cnt0_Q.D rev_req_cnt1_Q.D -------------------------------------------------------------------------------- Clock to Setup (tCYC) (nsec) (Clock: clk7d5) \ From r r r r r r \ e e e e e e \ l l l v v v \ a a a _ _ _ \ y y y r r r \ 5 6 7 e e e \ _ _ _ q q q \ Q Q Q _ _ _ \ . . . c c s \ Q Q Q n n y \ t t n \ 0 1 c \ _ _ _ \ Q Q Q \ . . . \ Q Q Q \ To \------------------------------------ ack_rev_Q.D 26.5 26.5 byte_cnt0_Q.D byte_cnt1_Q.D data_mode_Q.D host_clk_cnt0_Q.D host_clk_cnt1_Q.D host_clk_d1_Q.D host_clk_d2_Q.D our_addr_Q.D par_rx_rising_Q.D periph_ack_Q.D 26.5 26.5 periph_clk_Q.D reg_num0_Q.D reg_num1_Q.D reg_num2_Q.D relay0_Q.D relay1_Q.D relay2_Q.D relay3_Q.D relay4_Q.D relay5_Q.D 19.0 relay6_Q.D 19.0 relay7_Q.D 19.0 rev_req_cnt0_Q.D 19.0 19.0 19.0 rev_req_cnt1_Q.D 19.0 19.0 19.0 Path Type Definition: Pad to Pad (tPD) - Reports pad to pad paths that start at input pads and end at output pads. Paths are not traced through registers. Clock Pad to Output Pad (tCO) - Reports paths that start at input pads trace through clock inputs of registers and end at output pads. Paths are not traced through PRE/CLR inputs of registers. Setup to Clock at Pad (tSU) - Reports external setup time of data to clock at pad. Data path starts at an input pad and end at register D/T input. Clock path starts at input pad and ends at the register clock input. Paths are not traced through registers. Clock to Setup (tCYC) - Register to register cycle time. Include source register tCO and destination register tSU.