ngdbuild -p xc9572-15-pc84 -uc f:\power\power.ucf -dd .. f:\power\power.edn power.ngd
ngdbuild:  version M1.5.25
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc9572-15-pc84 -uc f:\power\power.ucf -dd ..
f:\power\power.edn power.ngd 

Launcher: Executing edif2ngd "f:\power\power.edn"
"F:\power\xproj\ver19\power.ngo"
edif2ngd:  version M1.5.25
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
Writing the design to "F:/power/xproj/ver19/power.ngo"...
Reading NGO file "F:/power/xproj/ver19/power.ngo" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "f:/power/power.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "power.ngd" ...

Writing NGDBUILD log file "power.bld"...

NGDBUILD done.

==================================================

hitop -f power.ngd -d power -s -l power.log -o power




Optimizer/Partitioner:  version M1.5.25
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Reading power.ngd
WARNING:nd7 - Signal 'FF_relay0_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay1_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay2_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay3_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay4_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay5_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay6_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay7_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
Using pinout defined in F:\power\fpanel.gyd.
Considering device XC9572-PC84.
    Flattening design..
    Timing optimization
    Timing driven global resource optimization    General global resource optimization........
    Re-checking device resources ...
    Mapping a total of 37 equations into 4 function blocks...............................
Design power has been optimized and fit into device XC9572-15-PC84.

==================================================

taengine -f power -l power.tim 


Timing Report Generator:  version M1.5.25
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Path tracing .......
The number of paths traced: 470.

Generating performance summary ...
Generating Pad-to-Pad delay section ...
Generating Clock-to-Output-Pad delay section ...
Generating Setup-To-Clock-At-Pad delay section ...
Generating Register-To-Register delay section ...
     Cycle time table for clock clk7d5 ...

power.tim has been created.

==================================================

hplusas6 -i power -s -a -l power.log -o fe_temp

Fitter1:  version M1.5.25
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.

==================================================

hprep6 -i fe_temp -r jed -a -l power.log -n power 

Programming File Generator:  version M1.5.25
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Signature length is limited to 4 characters, using 'powe'.

==================================================

xcpy power.jed f:\power\power.jed