#sccs "@(#)uts/kern/sys:hardware.h 1.2" /* Convergent Technologies - System V - Jun 1983 */ #ifndef hardware_h #define hardware_h #include #include /* 68010 status bits */ #define S_TRACE 0x8000 #define S_SUPV 0x2000 #define S_INTMASK 0x700 #define HIGH (S_SUPV|S_INTMASK) /* high priority supervisor mode (spl 7) */ #define LOW S_SUPV /* low priority, supervisor mode (spl 0) */ /* * WARNING: All these definitions are set up on the assumption * that they are operating on 16 bit quantities read/written from/to * the even address specified as the register address. * It is further assumed that all reads/writes of hardware registers * will be performed as 16 bit transfers to the even byte address. * It is believed that other schemes may work, but this is the way * these definitions are set up. */ /* General Control Register - GCR */ /* Write only. Uses address bits 16-18 of I/O address E4X0000 */ #define SYSERR_GCR_ADDR ((unsigned short *)0xE40000) /* EE+ */ #define SYSERR_ENABLE 0x8000 /* EE 1=enable NMI/BERR */ #define SYSERR_DISABLE 0x0000 /* EE 0=disable NMI/BERR */ #define PE_INT_GCR_ADDR ((unsigned short *)0xE41000) /* PIE+ */ #define PE_INT_ENABLE 0x8000 /* PIE 1=enable PE's */ #define PE_INT_DISABLE 0x0000 /* PIE 0=disable PE's */ #define PE_FRC_GCR_ADDR ((unsigned short *)0xE42000) /* BP+ */ #define PE_FRC_ENABLE 0x8000 /* BP 1=force bad parity */ #define PE_FRC_DISABLE 0x0000 /* BP 0=generate good parity*/ #define ROM_GCR_ADDR ((unsigned short *)0xE43000) /* ROMLMAP- */ #define ROM_DISABLE 0x8000 /* ROMLMAP 1=ROM disabled at low addr*/ #define ROM_ENABLE 0x0000 /* ROMLMAP 0=ROM mapped at low addr */ #define L1MD_GCR_ADDR ((unsigned short *)0xE44000) /* L1MD- */ #define L2MD_GCR_ADDR ((unsigned short *)0xE45000) /* L2MD- */ #define MD_DISCONNECT 0x8000 /* modem disconnected from line */ #define MD_CONNECT 0x0000 /* modem connected to line */ #define DNCT_GCR_ADDR ((unsigned short *)0xE46000) /* D/NCD1- */ #define DNLN1_CONNECT 0x0000 /* D/NCD1 0 => dialer connected to line 1 */ #define DNLN2_CONNECT 0x8000 /* D/NCD1 1 => dialer connected to line 2 */ /* Miscellaneous Control Register - MCR (4A0,000) (w) */ /* Write only. Uses most significant byte of 16 bit word */ #define MCR_ADDR ((unsigned short *)0x4A0000) #define CLRSINT 0x8000 /* CLRSINT- toggle from 1 to 0 and back to 1 to dismiss level 6, 60 hertz interrupt */ #define DMA_READ 0x4000 /* DMAR/W- 0 = disk DMA write 1 = disk DMA read */ #define LPSTB 0x2000 /* LPSTB+ toggle from 0 to 1 and back to 0 to strobe data to line printer */ #define MCKSEL 0x1000 /* MCKSEL- 0 = modem RX & TX selected 1 = programmable Baud Rate generator is selected */ #define LED3 0x800 /* LED3- 0 = on, 1 = off */ #define LED2 0x400 /* LED2- 0 = on, 1 = off */ #define LED1 0x200 /* LED1- 0 = on, 1 = off */ #define LED0 0x100 /* LED0- 0 = on, 1 = off */ /* Miscellaneous Control Register 2 - MCR2 (E20,000) (w) */ /* Write only. */ #define MCR2_ADDR ((unsigned short *)0xE20000) /* 15 is used to lock the floppy tape */ #define TLOCK 0x8000 /* 0 = lock, 1 = lock */ /* D12-14 are used to select tape stream */ #define TSEL2 0x4000 /* 1 = drive select 2 */ #define TSEL3 0x2000 /* 1 = drive select 3 */ #define TSIDSEL 0x1000 /* side select */ /* Defines for floppy tape stream select */ #define TSTRM1 0x4000 /* stream 1 select (TSIDSEL=0) */ #define TSTRM2 0x5000 /* stream 2 select (TSIDSEL=1) */ #define TSTRM3 0x2000 /* stream 3 select (TSIDSEL=0) */ #define TSTRM4 0x3000 /* stream 4 select (TSIDSEL=1) */ #define TSTRM5 0x6000 /* stream 5 select (TSIDSEL=0) */ #define TSTRM6 0x7000 /* stream 6 select (TSIDSEL=1) */ #define TSTRMSK 0x8fff /* stream code mask */ /* D11 is used for floppy tape motor control */ #define TMTR 0x0800 /* 0 = mtr on, 1 = mtr off */ /* D10 masks of interrupt from 2797 */ #define F_MASK 0x0400 /* Mask of floppy interrupts */ /* D8-9 are not used */ /* D5-7 are used for 2400 baud modem */ #define BAUD2400 0x0020 /* Select 2400 baud on modem */ #define DSPRST 0x0040 /* Not dsp reset */ #define LB_HB 0x0080 /* D2-4 are used for additional revision level information */ #define P3_P6 0x0010 /* Read phstat for this bit */ /* D0-1 are used for hard disk drives */ #define HDSEL3 0x0001 /* Hard disk head select bit 3 */ #define DDRIVE1 0x0002 /* Hard disk drive select bit 1 */ /* General Status Register - GSR (410,000) (r) */ /* Read only. Uses most significant byte of 16 bit word */ #define GSR_ADDR ((unsigned short *)0x410000) #define R_W_CYCLE 0x4000 /* R/W- 1=read cycle */ #define NPC_CYCLE 0x2000 /* NPC+ 1=DMA 0=processor */ #define PAGE_FAULT 0x1000 /* PF- 0=page fault */ #define PIE_STATE 0x400 /* PIE+ 1=PE's are enabled */ #define LPINTRQ 0x200 /* ??? 1=line printer intr (P3 only) */ #define USR_IO_FAULT 0x100 /* UIE- 0=user accessed I/O */ #define REV_LSB 0x8000 /* hardware revision - NC in P2 */ #define REV_MSB 0x0800 /* REV_LSB = PIE status in P3 */ /* Clear Status Register - CSR */ /* Read/Write. Uses most significant byte of 16 bit word */ /* Any access to this register clears the GSR and BSR0, BSR1 */ #define CSR_ADDR ((unsigned short *)0x4C0000) /* Bus Status Register 0 - BSR0 (430,000) (r) */ /* Read only. Uses 16 bit word */ /* Latched at the same time as the GSR and BSR1, also cleared by CSR */ #define BSR0_ADDR ((unsigned short *)0x430000) #define MMU_ERR 0x8000 /* 0=mmu error: processor or DMA page fault user writing to write protected page user accessing kernel space */ #define NOT_DGNT 0x4000 /* DKBG- 0 = disk DMA cycle */ #define NOT_XGT0 0x2000 /* EXP0BG- 0 = EXP0 DMA cycle */ #define NOT_XGT1 0x1000 /* EXP1BG- 0 = EXP1 DMA cycle */ #define NOT_XGT2 0x800 /* EXP2BG- 0 = EXP2 DMA cycle */ #define NOT_XGT3 0x400 /* EXP3BG- 0 = EXP3 DMA cycle */ #define UPPER_DATA_STROBE 0x200 /* UDS- 0 = Upper Data Strobe from 68010 */ #define LOWER_DATA_STROBE 0x100 /* LDS- 0 = Lower Data Strobe from 68010 */ #define PA23 0x80 /* PA23 Processor Address 23 */ #define PA22 0x40 /* PA22 Processor Address 22 */ #define LA21 0x20 /* A21 Logical Address 21 */ #define LA20 0x10 /* A20 Logical Address 20 */ #define LA19 0x8 /* A19 Logical Address 19 */ #define LA18 0x4 /* A18 Logical Address 18 */ #define LA17 0x2 /* A17 Logical Address 17 */ #define LA16 0x1 /* A16 Logical Address 16 */ #define A23_A16_MASK 0xff /* mask of A23 to A16 */ #define A21_A16_MASK 0x3f /* mask of A21 to A16 */ /* Bus Status Register 1 - BSR1 (440,000) (r) */ /* Read only. Uses all of 16 bit word */ /* Latched at the same time as the GSR and BSR0, also cleared by CSR */ #define BSR1_ADDR ((unsigned short *)0x440000) #define A15_A00_MASK 0xffff /* mask of A15 to A0 */ /* Off-board addressing registers */ #define MY_SLOT ((slot_t *)0) /* lie about it */ /* Hardware Register Definitions */ #define KSTACK 0x70900 /* kernel stack address */ #define PG_USER 0x70 /* virtual page no of user table */ /* mcr_save must be written to whenever the real MCR is written to. */ extern ushort mcr_save; /* defines to manipulate the LED's */ /* where x is any sum of LED0, LED1, LED2, LED3 */ #define led_init() led_off(LED0|LED2|LED1|LED3) #define led_on(x) *MCR_ADDR = (mcr_save &= ~(ushort)(x)) #define led_off(x) *MCR_ADDR = (mcr_save |= (ushort)(x)) #define led_toggle(x) *MCR_ADDR = (mcr_save ^= (ushort)(x)) /* address in vector table of a pointer to the CDT. */ #define pCDT 0x3F8 /* software leaves pointer in penultimate int vector */ /* CDT signature long word */ #define SIG1 0x45504A52 /* Format - to be used by crash in analyzing dump * * 0000 - 003F: machine registers * 0040 - 0041: GSR * 0042 set to zero * 0043 - 0045: BSR * 0046 - 0845 memory map registers * 0846 - 08C5 CDT */ /* Displacements from the start of a crash dump plus SAVEAREA. */ #define SAVEAREA 0x0000 #define SVREGS 0x0000 #define SVGSR 0x0040 #define SVBSR 0x0042 #define SVMAP 0x0046 #define SVCDT 0x0846 /* Format of the CDT (128 bytes) * signature 4 bytes * lbolt 4 bytes * time of day 4 bytes * reason 1 byte * (0 = panic, 1 = reset, 2 = poweron) * boot media 1 byte * (2 = fd, 1 = syq, 0 = hd) * panic string 114 bytes #define CdtSig 0x00 #define CdtLbolt 0x04 #define CdtTOD 0x08 #define CdtReason 0x0C #define CdtMedia 0x0D #define CdtPanic 0x0E */ #define SZPANIC 114 #define SZCDT 128 struct CDT { unsigned int CdtSig; time_t lbolt; time_t time; char CdtReason; char CdtMedia; char CdtPanic[SZPANIC]; }; /* Reasons */ #define PANIC 0 #define RESET 1 #define POWERON 2 /* Address the loader is loaded at */ #define LOADADDR 0x70000 #define BOOTCDT LOADADDR-SZCDT #endif hardware_h