#sccs "@(#)uts/kern/sys:modem.h 1.1" /* ------------------------------------------------------------------------- | This include file contains constant to control the 882A Switched | | Capacitor Modem (SCM). | ------------------------------------------------------------------------- --------------------------------------------------------- | Addresses of SCM Control registers, register 7 | | does not exist. | | W/R at the end defines a Read or Write register. | --------------------------------------------------------- */ #define SCM_0W_Control ((unsigned short *) 0xE60000) #define SCM_1W_Control ((unsigned short *) 0xE61000) #define SCM_2R_Control ((unsigned short *) 0xE62000) #define SCM_3R_Control ((unsigned short *) 0xE63000) #define SCM_4W_Control ((unsigned short *) 0xE64000) #define SCM_5W_Control ((unsigned short *) 0xE65000) #define SCM_6W_Control ((unsigned short *) 0xE66000) #define SCM_8W_Control ((unsigned short *) 0xE68000) #define SCM_9W_Control ((unsigned short *) 0xE69000) #define SCM_10R_Control ((unsigned short *) 0xE6A000) /* --------------------------------------------------------- | Bit definition for write control register 0. | | Modem line control from terminal and telephone | | interfaces. | --------------------------------------------------------- */ #define SCM_RingEnable_Wr0 0x80 #define SCM_TalkMode_Wr0 0x40 #define SCM_OffHook_Wr0 0x20 #define SCM_DataMode_Wr0 0x10 #define SCM_AsyncMode_Wr0 0x08 #define DTRMD 0x04 #define SCM_TurnOnDTR_Wr0 0x04 #define SCM_LowPower_Wr0 0x02 /* Reset for normal operation */ #define LOWPOWER 0x02 #define SCM_PowerReset_Wr0 0x01 /* Set and reset for normal operation */ #define SCM_ResetDone_Wr0 0x00 /* --------------------------------------------------------- | Bit definition for write control register 1. | | Customer control and modem test controls. | --------------------------------------------------------- */ #define InternalClock_SCM_Wr1 0x00 #define ExternalClock_SCM_Wr1 0x40 #define VoiceMode_SCM_Wr1 0x20 #define VOICEJACK 0x20 #define BAUD300 0x00 #define BAUD1200 0x10 #define Baud300_SCM_Wr1 0x00 #define Baud1200_SCM_Wr1 0x10 #define Baud2400_SCM_Wr1 0x10 /* also need R8b3 to be set */ /* Loopback test selection */ #define RemoteDigtal_SCM_Wr1 0x08 #define LocalAnalog_SCM_Wr1 0x04 #define LocalDigital_SCM_Wr1 0x02 #define SelfTest_SCM_Wr1 0x01 /* --------------------------------------------------------- | Bit definition for read control register 2 | | Modem status to terminal interface. | --------------------------------------------------------- */ #define FailedSelfTest_SCM_Rr2 0x80 #define SCMinTestMode_SCM_Rr2 0x40 #define SCMinDataMode_SCM_Rr2 0x20 /* an incoming call was answered */ #define DSRisOn_SCM_Rr2 0x10 #define BaudrateMask_SCM_Rr2 0x0C #define at300Baud_SCM_Rr2 0x00 #define at1200Baud_SCM_Rr2 0x04 #define at2400Baud_SCM_Rr2 0x0C #define DataValid_SCM_Rr2 0x02 /* set after modem handshake */ #define CTSisOn_SCM_Rr2 0x01 /* --------------------------------------------------------- | Bit definition for read control register 3 | | Modem status to lamps and relays. | --------------------------------------------------------- */ #define DigitalTestActive_SCM_Rr3 0x80 /* local or remote */ #define SlfTestActive_SCM_Rr3 0x40 #define SendDataState_SCM_Rr3 0x20 /* input to modulator */ #define ReceiveDataState_SCM_Rr3 0x10 /* output from demodulator */ #define EnergyOnLine_SCM_Rr3 0x08 #define ModemInUse_SCM_Rr3 0x04 #define SwitchFromPhoneToModem_SCM_Rr3 0x02 #define RingRelayIsSet_SCM_Rr3 0x01 /* --------------------------------------------------------- | Bit definition for write control register 4 | | Options: Asynchronous/synchronous converter | | and handshaking. | --------------------------------------------------------- */ #define SetSynchMode_SCM_Wr4 0x80 /* 1200 and 2400 baud only */ #define SetAsyncMode_SCM_Wr4 0x00 #define SetOptionAsync_SCM_Wr4 0x40 #define Set6DataBits_SCM_Wr4 0x20 #define Set7DataBits_SCM_Wr4 0x10 #define Set8DataBits_SCM_Wr4 0x00 #define Set9DataBits_SCM_Wr4 0x30 #define NormalBandMode_SCM_Wr4 0x00 #define ReverseBandMode_SCM_Wr4 0x04 #define TxLowBandMode_SCM_Wr4 0x08 /* Force originate only */ #define TxHighBandMode_SCM_Wr4 0x0C /* Force answer only */ #define PrivateHandshake_SCM_Wr4 0x02 #define CCITTAnswerTone_SCM_Wr4 0x01 #define B212AnswerTone_SCM_Wr4 0x00 /* --------------------------------------------------------- | Bit definition for write control register 5 | | Options: CCITT and disconnect. | --------------------------------------------------------- */ #define Wr5_NormalOperations_SCM_Wr 0x00 #define CCITTDSR_SCM_Wr5 0x80 #define B212DSR_SCM_Wr5 0x00 #define CCITT2100HzTone_SCM_Wr5 0x40 #define B212No2100HzTone_SCM_Wr5 0x00 #define Set1800GuardBand_SCM_Wr5 0x20 #define B212NoGuardBand_SCM_Wr5 0x00 #define NoAutoDataMode_SCM_Wr5 0x10 #define DTRAutoDataMode_SCM_Wr5 0x00 /* Modem disconnect options */ #define SendNoSpaceDisconnect_SCM_Wr5 0x08 #define SendSpaceDisconnect_SCM_Wr5 0x00 /* send space for 4 seconds */ #define IgnoreSpaces_SCM_Wr5 0x04 #define SpaceRcvdDisconnect_SCM_Wr5 0x00 #define IgnoreLossOfLCD_SCM_Wr5 0x02 #define LossOfLCDDisconnect_SCM_Wr5 0x00 #define IgnoreRemoteDigRequest_SCM_Wr5 0x01 #define AcceptRemoteDigRequest_SCM_Wr5 0x00 /* --------------------------------------------------------- | Bit definition for write control register 6 | | Data and timing output clamps and chip test. | --------------------------------------------------------- */ #define Wr6_NormalOperations_SCM_Wr6 0x00 #define SetTxDataToMark_SCM_Wr6 0x80 #define SetTxTimingToMark_SCM_Wr6 0x40 #define SetRxDataToMark_SCM_Wr6 0x20 #define SetRxTimingToMark_SCM_Wr6 0x10 /* --------------------------------------------------------- | Bit definition for write control register 8 | | Tranceiver control register. | --------------------------------------------------------- */ #define Wr8_NormalOperations_SCM_Wr8 0x20 #define TxScramblerBypass_SCM_Wr8 0x80 #define RxDescramblerBypass_SCM_Wr8 0x40 #define Set2400Baud_SCM_Wr8 0x08 /* R1b4 should also be set */ #define ForceTxMarks_SCM_Wr8 0x04 #define Force2100Hz_SCM_Wr8 0x02 #define Force1800Hz_SCM_Wr8 0x01 /* --------------------------------------------------------- | Bit definition for write control register 9 | | Transceiver control register II. | --------------------------------------------------------- */ #define Wr9_NormalOperations_SCM_Wr9 0x00 #define SendDoubleDotting_SCM_Wr9 0x01 /* --------------------------------------------------------- | Bit definition for read control register 10 | | Transceiver status register. | --------------------------------------------------------- */ /* SCM handshake indicators */ #define SendingSpaces_SCM_Rr10 0x80 #define DigLoopbackTest_SCM_Rr10 0x40 /* is set in the modem requesting the test */ #define FSKScramMarkReceived_SCM_Rr10 0x20 /* stays set in data mode */ #define AnsToneReceived_SCM_Rr10 0x10 /* stays set in data mode */ /* Received data indicators, these bits reflect the current state of the receiver, values are not latched. */ #define FSKUnscramMarkRcving_SCM_Rr10 0x08 #define PSKUnscramMarkRcving_SCM_Rr10 0x04 #define PSKScramMarkRcving_SCM_Rr10 0x02 #define DoubleDottingRcving_SCM_Rr10 0x01